Protection structures against electrostatic discharges (electrostatic discharge (ESD) protection structures) are widely used in semiconductor technologies in order to protect circuit blocks against electrostatic discharge during mounting and operation. These ESD protection structures are intended to be able to carry away discharge currents rapidly and reliably in order to prevent destruction of the circuit blocks to be protected by the discharge currents.
The protection properties of the ESD protection structures are specified here with reference to ESD test standards. Besides ESD test standards at the component or IC level (integrated circuit) such as, for example, the test according to the human body model (HBM), which is standardized for instance by the ESD Association & JEDEC Solid State Technology Association, ESD test standards at the system level, in particular, make stringent requirements of the ESD protection structures. One common ESD standard at the system level is IEC 61000-4-2. The particularly stringent requirements made of ESD protection structures by ESD standards at the system level become clear for example upon comparison of the peak currents and rise times that result from the standards at a loading voltage of 2 kV. While an ESD pulse according to the human body model (HBM) entails a peak current of approximately 1.3 A with a rise time of approximately 2-10 ns at a loading voltage of 2 kV, a peak current of above 6 amperes with a rise time of typically below 1 ns results at a loading voltage of 2 kV in the case of an ESD pulse according to the IEC standard. Consequently, particular requirements such as rapid reaction time and high robustness are made particularly of ESD protection structures in integrated circuits which are intended to satisfy requirements in respect of ESD test standards at the system level.
It is an object of the invention to specify an integrated circuit comprising an ESD device which satisfies the above requirements.